This application relates, in general, to semiconductor devices and, more particularly, to improved means and method for providing merged complementary bipolar and complementary MOS devices in an integrated circuit. As used herein the word "CBICMOS" is intended to refer to integrated complementary bipolar and complementary MOS devices.
MOS devices (MOSFETS) and bipolar devices have desirable but different characteristics. The wafers, masks and processes sequences for forming MOS and bipolar devices are, in general, different. Processes and structures for forming complementary MOS devices (CMOS) on the same semiconductor wafer are well known in the art. Also, processes and structures for forming BIMOS devices, that is CMOS and NPN bipolar devices, on the same wafer are known. Other processes and structures for forming complementary (NPN and PNP) bipolar devices on the same wafer are also known. However, satisfactory processes and structures for forming complementary MOS and complementary bipolar devices (CBICMOS) on the same wafer have not been available in the prior art. It is especially difficult to form CBICMOS devices on the same wafer in a space economical and process compatible fashion. A need continues to exist for integrated CBICMOS devices because of the great advantage that such devices can provide for implementation of high speed, low power complex integrated circuits.
Accordingly, it is an object of the present invention to provide an improved means and method for complementary bipolar and complementary MOS devices in a common substrate where the devices are merged in a space economical manner.
It is a further object of the present invention to provide an improved means and method for forming CBICMOS devices on a common substrate by a common sequence of masks and process steps.
It is a still further object of the present invention to provide an improved means and method for forming CBICMOS devices on a common substrate where the N and P type devices are laterally isolated but so arranged as to be readily interconnectable by a single conductor layer.